Rivos is seeking highly motivated candidates for CPU power design, modeling, and optimization. The ideal candidate will possess in-depth experience in full-spectrum silicon power reduction, including solid power analysis, benchmarking, and design optimization at all levels (architecture, micro-architecture, implementation, and binning) for CPU blocks. Responsibilities include driving power design tasks across various teams, modeling use-cases and workloads, analyzing power-performance trade-offs, creating test vectors, performing power simulations and analysis, collaborating with CAD and physical design teams, and influencing SoC power. The role requires a strong understanding of CPU architectures, workload modeling, Verilog/SystemVerilog, silicon design flow, and EDA tools for power simulations.