The Senior IC Layout Designer will collaborate with IC Design Engineers across three design sites: the United States, the United Kingdom, and Switzerland, to translate circuit schematics into physical layouts. This role involves working with technology engineers to incorporate circuit components, such as transistors, resistors, capacitors, and test structures, into the layout. The designer will also be responsible for validating the completed physical layout using CAD tools like Cadence Layout and Schematic editor and Mentor Calibre DRC and LVS. Furthermore, they will perform all essential tasks for preparing and taping out the verified layout database to the mask shop.