NXP is seeking a 2025 Intern - Design Verification Engineer for their Wireless group. The role involves creating DV test benches, developing test plans and cases, generating DV coverage, and collaborating with architecture and RTL designers to develop new IP. Candidates should be Masters’ students in electronic/computer engineering with strong familiarity in UVM, SystemVerilog, Verilog HDL, digital design EDA tools (DC, PT, Formality), and 1+ years of experience in IP simulation and debug using VCS and Verdi. Familiarity with IC design flow is also required.