This internship position for a Design Verification Engineer in Wireless involves creating DV test benches, developing test plans and cases, generating DV coverage, and collaborating with architecture and RTL designers to develop new IPs. Candidates should be Master's students in electronic/computer engineering with strong familiarity in UVM, SystemVerilog, Verilog HDL, digital design EDA tools (DC, PT, Formality), and experience in IP simulation and debug using VCS and Verdi. Familiarity with IC design flow is also required.