CPU Logic Design Engineer
Job Summary
Job Description
- PhD in Electrical Engineering or Computer Science
- RTL design experience (SystemVerilog or VHDL)
- Microarchitecture experience
- Deliver designs meeting PPA goals
- Design/microarchitecture experience
2 skills required
Job Details
Minimum qualifications:
- PhD degree Electrical Engineering or Computer Science, or equivalent practical experience.
- Experience digital logic at Register Transfer Level (RTL) level using SystemVerilog or VHDL.
Preferred qualifications:
- Experience in Design/microarchitecture.
About the job
The ML, Systems & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
- Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
- Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture enhancements. Facilitate final decision making.
- Deliver designs meeting Power, performance, and area (PPA) goals with production quality.
- Become familiar with techniques for at least one processor functional block. Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.
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