Digital Design Engineer

Company:

Job Area:

General Summary:

Minimum Qualifications:

• Responsibilities

  • Front-End/Digital design implementation of Sensor/Mixed signal digital blocks

  • RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules.

  • Work with SoC power management team for power sequencing requirements and system level considerations

  • Work with functional verification team on test-plan development and debug.

  • Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA.

  • UPF writing, power aware equivalence checks and low power checks.

  • DFT insertion and ATPG analysis for optimal SAF, TDF coverage.

  • Provide support to SoC integration and chip level pre/post-silicon debug.

• Skills & Experience

  • MTech/BTech in EE/CS with hardware engineering experience of 4+ years.

  • Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA.

  • Experience with post-silicon bring-up and debug is a plus.

  • Able to work with teams across the globe and possess good communication skills.

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