Job Details:

Job Description: 

Seize the opportunity to work with the team responsible for RTL logic design and development of chipsets for PCs millions of people around the world will use. The Chipsets Logic Team, CLIPS is responsible for developing soft IPs, subsystems and gaskets for Intel Client products.

This job requisition is to seek an experienced, disciplined and collaborative design verification engineer as Intel Contract Employee (ICE) in Malaysia.

• As a member of the Chipsets Logic Design Verification team, you will work closely with IP architects to define and develop verification testbench and building RTL models for verification.

• You will be validating and verifying the functionality of new architectural features of next generation designs by developing testplan, tests content or test tools.

• You will be finding and implementing corrective measures for failing RTL tests, analyzes and uses results to modify testing.

• Your influence will cross organizational boundaries with our manufacturing and validation partners.

• Your expertise will grow as you debug and resolve issues on system platforms using software and RTL simulation tools.

Qualifications:

• The candidate must possess a minimum of Bachelor Degree in Electronics Engineering, Computer Engineering, Computer Science or equivalent.
• The candidate must have demonstrated the ability to solve challenging technical problems with good communication skills.
• The candidate must also have demonstrated strong ethical standards.

Minimum requirements:

• 2+ years of relevant pre-silicon verification/logic design experience.
• Experienced with various tools and methodologies including but not limited to: System Verilog, Python/Perl/Shell scripting, power-aware simulation with VCS/Synopsys tools, RTL model build, design-for-test, design-for-verification.

Preferred requirements:

• Experienced in developing test plan and contents and coverage points for validation purpose based on High Level Architecture specifications.
• Experienced in VLSI or Structural and Physical design flow and methodology, SIP and HIP interoperability validation.
• Experienced in Power-aware design and validation flows.
• Experienced in AMBA, UFS, SPI, USB, PCI express or any industry standard BUS protocol.
• Strong Chipset or CPU level understanding required on power consumption, power estimation and low power design methods.

          

Job Type:

Intel Contract Employee

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Malaysia, Kulim

Business group:

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.