Senior Lead/Staff RTL Design Engineer

13 Hours ago • 5 Years +

Job Summary

Job Description

As a Senior Lead/Staff RTL Design Engineer at Qualcomm, you will be responsible for logic design, micro-architecture, and RTL coding. You will work on complex SoC designs, synthesis, and timing analysis. The role requires hands-on experience with Verilog/System-Verilog and knowledge of AMBA protocols, clocking/reset/debug architecture, and peripherals. You will collaborate with various teams, including DFT and STA teams, and will be involved in low-power SoC design, multi-clock designs, and asynchronous interfaces. Experience with tools like DesignCompiler, Genus, FusionCompiler, and Primetime is also essential.

Must have:

5+ years experience in logic design/micro-architecture/RTL coding
Hands-on experience with SoC design, synthesis and timing analysis
Experience in Verilog/System-Verilog is a must
Knowledge of AMBA protocols
Hands on experience in Low power SoC design is required

Good to have:

Understanding of constraint development and timing closure
Experience in Synthesis / Understanding of timing concepts

2 skills required

2 skills required for this role

Add these skills to join the top 1% applicants for this job

fpga

cross-functional

Job Details

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Principal Duties and Responsibilities:

5+ Years of Experience in Logic design /micro-architecture / RTL coding
Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs.
Experience in Verilog/System-Verilog is a must.
knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.
Work closely with the SoC DFT, Physical Design and STA teams
Hands on experience in Low power SoC design is required
Hands on experience in Multi Clock designs, Asynchronous interface is a must.
Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required.
Understanding of constraint development and timing closure is a plus.
Experience in Synthesis / Understanding of timing concepts

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