Job Details:

Job Description: 

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans,

Qualifications:

Minimum Qualifications:

• BE/Btech/MTech with 6 Plus years of experience

Preferred Qualifications:

• Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.

• OVM/UVM, System Verilog, constrained random verification methodologies.

• The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).

• Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.

• Create plans and tests for validating portions of a complex microarchitecture using written specs, RTL code, Firmware and other tests as a guide

• Experienced with the architecture, microarchitecture and Power Management flows and debugging failures to the root cause

• Develop and utilize various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design

• Participate in the debug of failures on silicon and develop new testing strategies to detect these failures on RTL models

• Develop tools and methods to streamline validation of PM flows, PM HW/FW interactions, and SOC level validation to deliver highest quality design in shortest time possible.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.