Silicon PCIe Bringup and Validation Engineer
Job Summary
Job Description
The Silicon PCIe Bringup and Validation Engineer role focuses on initiating and validating PCIe subsystems within Rivos SOC designs. This requires a deep understanding of advanced PCIe designs for server applications, encompassing physical design, logic, performance, system, and software. Key responsibilities include generating tests, setting up test infrastructure, planning and executing bringup processes, and developing and implementing validation plans for PCIe systems. The company is seeking candidates for technical lead or senior technical staff positions.
Must have:
- Lead PCIe subsystem silicon bringup plans
- Collaborate with cross-functional teams
- Debug and root-cause issues
- In-depth knowledge of PCIe subsystem architecture
- Experienced in C/C++ and Python
- Knowledge of verification methodologies
- Experience in silicon debug
Good to have:
- Work with vendors and partners
- Drive continuous improvement
- Maintain up-to-date knowledge of technology
- Ability to work well in a team
3 skills required
Job Details
The role of the Silicon PCIe Bringup and Validation Engineer involves the initiation and validation of the PCIe subsystems within Rivos SOC design. This position demands a comprehensive grasp of cutting-edge PCIe design tailored for server applications, covering aspects such as physical design, logic, performance, system, and software. Responsibilities includes test generation, configuring test infrastructure, planning and executing bringup processes, and developing and executing validation plans specifically for PCIe systems. Currently, the intention is to fill technical lead or senior technical staff positions for this role.
Responsibilities
- As a lead, you will lead an engineering team responsible for designing, implementing and executing a PCIe subsystem silicon bringup plans, including functional and performance tests, to validate the subsystem for the silicon product to meet the product requirements.
- Collaborate with cross-functional teams including design, architecture, firmware, and software to ensure successful subsystem integration and validation.
- Work with vendors and partners to ensure successful subsystem bringup and validation, including reviewing and providing feedback on vendor documentation, and coordinating with vendor support teams.
- Debug and root-cause issues found during subsystem bringup and validation, and work with cross-functional teams to implement corrective actions.
- Drive continuous improvement of subsystem bringup and validation processes and methodologies, including automation, tool development, and documentation.
- Maintain up-to-date knowledge of the subsystem technology and industry trends.
Requirements
- In-depth knowledge of system architecture, performance/power, and software of PCIe subsystem for server applications.
- Experienced level knowledge C/C++ and Python.
- Relevant knowledge of verification methodologies, Verilog simulation, waveform viewers, and emulation.
- Experience in silicon debug for logic, software, and physical issues
- Strong ability to triage issues and develop environment and tools.
- Excellent skills in problem solving, written and verbal communication, excellent organization skills, and highly self-motivated.
- Ability to work well in a team and be productive under aggressive schedules.
Education & Experience
- PhD, Master’s Degree or Bachelor’s Degree with more than 5 years of experience in PCIe technical subject area.
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